1. Field of the Invention
The present invention relates generally to compensation for the effects of temperature changes, voltage changes and noise on a delay locked loop (DLL). More particularly, the present invention relates to providing a buffer of delay elements at a boundary of an adjustable delay line of a DLL during initialization of the DLL.
2. State of the Art
Many high speed electronic systems possess critical timing requirements which dictate the need to generate a periodic clock wave form having a precise time relationship with respect to a reference signal. The improved performance of integrated circuits (ICs) and the growing trend to include several computing devices or system components on the same board present a challenge with respect to synchronizing the time frames of all of the components.
For optimal performance, the operation of all components in a system should be highly synchronized (e.g., signal skew, or the time difference between the significant edges of the internally generated clocks of all the components, should be minimized). Merely feeding the reference clock of the system to every component is insufficient because different components may have different manufacturing parameters which, when taken together with factors such as ambient temperature, voltage and processing variations, may lead to large differences in the phases of the respective component clock signals.
In conventional ICs, synchronization is achieved by using a delay locked loop (DLL) circuit to detect a phase difference between clock signals of the same frequency and to produce a digital signal related to the phase difference. By feeding back the phase difference-related signal to circuitry controlling a plurality of delay elements in a delay line, the timing of one clock signal, such as a system clock signal, is advanced or delayed until its rising edge is coincident with the rising edge of a second clock signal, such as a component clock signal.
The operation of a conventional digital DLL is shown in FIGS. 1 and 2. In FIG. 1, clock input buffer 2, delay line 4, and data output buffer 8 constitute an internal clock path. Delay line 4 is a variable delay generator with a logic-gate chain. Modeled delay line 6 is coupled to modeled circuits 10, 12 and 14 which emulate the internal clock path components. Modeled circuits include modeled output buffer 10, with modeled load capacitance 14 and modeled clock buffer 12. The modeled components 6, 10, 12 and 14 constitute a modeled clock path having substantially the same delay time as the internal clock path. Shift register 16 is used for activating a number of delay elements in both delay lines 4 and 6 based on a command generated by a phase comparator 18.
The phase comparator 18 compares the modeled clock and the external clock phases which differ by one cycle. This comparison is illustrated in FIG. 2. The external clock signal 20 may be divided down in a divider 22 to produce a divided-down external signal 24. Signal 26 is the signal at the output of modeled delay line 6. Signal 28, which is generated inside phase comparator 18, is a modeled output buffer signal 26 delayed by one delay unit. If both signals 24 and 26 go high before 20 goes low, this means that the output clock is too fast and the phase comparator 18 outputs a shift left (L) command to the shift register 16, as illustrated in FIG. 2. The shift register 16 shifts the tap point of the delay lines 4 and 6 by one step to the left, increasing the delay. Conversely, if both signals 26 and 28 go high after signal 24 goes low, this means that the output clock is too slow and phase comparator 18 outputs a shift right (R) command to the shift register 16. The shift register 16 shifts the tap point of the delay lines 4 and 6 by one step to the right, decreasing the delay. If signal 24 goes low between the time signals 26 and 28 go high, the internal cycle time is properly adjusted and no shift command is generated.
One drawback of conventional DLLs, however, occurs when a DLL is placed in a state of minimum or maximum delay. A state of minimum delay occurs when the delay between the input and output clock signals is as close to zero as allowed by the parameters of the delay line (i.e., when the tap point is at the beginning of the delay line). In this case, if the DLL attempts to decrease the delay, such decrease would be impossible because the delay line is already at a minimum delay. Conversely, maximum delay occurs when the DLL is as close to maximum delay as allowed by the parameters of the delay line (i.e., when the tap point is at the end of the delay line). In the latter case, if the DLL attempts to increase the delay, such increase would be impossible because the delay caused by the delay line is already at the maximum delay permitted. In these minimum and maximum delay states, an attempt to shift beyond the minimum or maximum delay boundary causes the DLL to reset and attempt to relock on another delay state. If this occurs during a xe2x80x9creadxe2x80x9d operation, the output to the data output circuitry (DQ) may be out of phase with the input clock. When the input and output clocks are out of phase, the signal skew increases and the tAC, or time from when a transition occurs on the system clock to the time when the data comes through DQ, is unstable until the DLL locks again. Increased skew and unstable tAC may result in faulty data transfer and undesired delay.
Temperature and voltage changes, as well as noise generated through operation of an integrated circuit system, may cause a DLL""s signal delay setting to shift during operation. If the DLL delay line settings are near the minimum or maximum boundaries of the delay line, these signal timing changes may cause the DLL to shift beyond the minimum and maximum boundaries and result in the DLL attempting to reset while data is being transferred.
One approach to compensating for DLL shifts beyond maximum or minimum boundaries is to construct a wrap-around loop, so that when the DLL is at minimum delay, the delay line shifts around to the maximum delay. This approach, however, involves excess circuitry because DLL delay lines are conventionally of sufficient length to adapt to system changes and noise without exceeding the delay line""s boundaries. Furthermore, a wrap-around DLL achieves a phase lock with a signal harmonic rather than the direct signal, which is also less than ideal.
Another approach to compensating for DLL shifts beyond maximum or minimum boundaries is to add a correction latch to a conventional DLL circuit which latches an activation signal upon detection of a state of minimum delay and generates an override shift left (or disabled shift right) signal, causing the delay line to shift towards more delay. The correction latch is then reset once the system itself generates a shift left signal and resumes normal operation. At maximum delay, the reset mechanism resets the shift register to a state of minimum delay. This approach is described in more detail in LIN, FENG, et al., A Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM, IEEE Journal of Solid-State Circuits, Vol. 34, No. 4, April 1999, pp. 565-568, the disclosure of which is hereby incorporated herein by reference. This approach, however, also results in undesired delays in adjusting for shifts beyond the delay locked loop parameter boundaries.
Therefore, it is desirable to improve the performance of DLLs by reducing the delays caused by shifting beyond the minimum and maximum tap settings of the DLL delay line. It is further desirable to compensate for signal timing changes caused by changes in temperature, voltage and noise levels which may result in the DLL delay line attempting to shift beyond its minimum and maximum boundaries.
The present invention provides a unique method and circuitry for alleviating many of the problems associated with conventional DLLs by providing a buffer region near the minimum or maximum boundaries, or both, of a DLL delay line in which a DLL is not permitted to lock during initialization. In this way, delays due to signal timing shifts from temperature, voltage and noise changes in the system subsequent to initialization will be significantly less likely to force the signal timing beyond the actual delay line boundary.
According to an embodiment of the invention, rather than allowing the DLL to lock on any point on the delay line during initialization or reset, the DLL is configured to preclude one or more tap settings near the minimum or maximum delay line tap settings, or both, as possibilities for locking. When powering-up or resetting the DLL, the DLL circuit is precluded from locking to the first few or the last few delays in the adjustable delay line. If the desired lock point is inside this range, the DLL is forced to lock to the next valid clock cycle. Once the power-up/reset is complete, there will be a buffer of delay elements between the lock point and the boundaries of the adjustable delay line. This buffer of delay elements provides the DLL with room to shift in response to temperature and voltage changes, and noise induced by the operation of the part, while avoiding the DLL reset that occurs at either end of the adjustable delay line. During operation of the DLL other than initialization, the previously precluded tap settings at either end of the delay line are available for use if necessary.
A method of initializing a delay locked loop is disclosed wherein the delay locked loop is precluded from locking into at least one tap setting on a delay line during initialization, but permitted to shift to the delay element associated with that tap setting at times other than initialization. In one embodiment, the tap setting is adjacent the minimum delay boundary of the delay line. In another embodiment, the tap setting is adjacent the maximum delay boundary of the delay line. In yet another embodiment, the at least one tap setting is adjacent both the minimum and maximum delay boundaries of the delay line. The at least one tap setting may include multiple tap settings adjacent either or both of the delay boundaries.
An electronic system is disclosed comprising a processor, a memory device, an input, an output and a storage device, one or more of which include at least one delay locked loop configured to preclude one or more tap settings during initialization. A semiconductor wafer is disclosed having fabricated thereon at least one delay locked loop configured according to one or more embodiments of the invention.